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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
4M Late Write 2.5 V I/O
The MCM69L738A/820A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69L820A organized as 256K words by 18 bits, and the MCM69L738A organized as 128K words by 36 bits wide are fabricated in Motorola's high performance silicon gate BiCMOS technology. The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is available at the falling edge of the CK clock. The RAM uses 2.5 V inputs and outputs. The synchronous write and byte enables allow writing to individual bytes or the entire word. * * * * * * * * * Byte Write Control Single 3.3 V + 10%, - 5% Operation 2.5 V I/O (VDDQ) Register to Latch Synchronous Operation Asynchronous Output Enable Boundary Scan (JTAG) IEEE 1149.1 Compatible Differential Clock Inputs Optional x18 or x36 organization MCM69L738A/820A-8.5 = 8.5 ns MCM69L738A/820A-9 = 9 ns MCM69L738A/820A-9.5 = 9.5 ns * Sleep Mode Operation (ZZ Pin) * 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package
MCM69L738A MCM69L820A
ZP PACKAGE PBGA CASE 999-01
This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 8/13/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 1
FUNCTIONAL BLOCK DIAGRAM
ADDRESS REGISTERS DATA IN REGISTER DQ DATA OUT LATCH
SA
MEMORY ARRAY
SW SBx
SW REGISTERS
CONTROL LOGIC
CK G
SS
SS REGISTERS
PIN ASSIGNMENTS TOP VIEW MCM69L738A
1 A B C D E DQc F G DQc H J K L DQd M VDDQ DQd N P R T U DQd DQd NC NC DQd DQd SA NC VSS VSS VSS SW SA SA VSS VSS VSS VSS SA TDO DQa VDDQ DQa DQa SA NC DQa DQa NC ZZ N P R T NC U SA SA TDI NC TCK SA TDO SA ZZ VDDQ TMS NC VDDQ DQd SBd CK SBa DQa DQa M VDDQ DQb DQb NC NC NC DQb SA VSS VSS VSS SW SA SA VSS VSS VSS VSS NC VDDQ DQa NC SA NC DQa NC DQc DQc DQc SBc VSS NC VSS NC NC VDD CK SBb VSS NC VSS DQb DQb DQb DQb H J K L DQc VSS VSS SS G VSS VSS DQb DQb F G NC DQb DQb NC SBb VSS NC VSS VSS NC NC VDD CK CK VSS VSS NC VSS SBa NC DQa DQa NC VDDQ DQc DQb VDDQ VDDQ NC NC DQc 2 SA NC SA DQc 3 SA SA SA VSS 4 NC NC VDD NC 5 SA SA SA VSS 6 SA NC SA DQb 7 VDDQ NC NC DQb A B C D E NC VDDQ DQb NC VSS VSS SS G VSS VSS NC DQa DQa VDDQ 1 VDDQ NC NC DQb 2 SA NC SA NC
MCM69L820A
3 SA SA SA VSS 4 NC NC VDD NC 5 SA SA SA VSS 6 SA NC SA DQa 7 VDDQ NC NC NC
VDDQ VDD DQd DQd
VDD VDDQ DQa DQa
VDDQ VDD NC DQb DQb NC
VDD VDDQ NC DQa DQa NC
VDD VDD SA TDI SA TCK
VDD VDD
VDDQ TMS
NC VDDQ
MCM69L738A*MCM69L820A 2
MOTOROLA FAST SRAM
MCM69L738A PIN DESCRIPTIONS
PBGA Pin Locations 4K 4L (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T 5L, 5G, 3G, 3L (a), (b), (c), (d) 4E 4M 4U 3U 5U 2U 7T 4C, 2J, 4J, 6J, 4R, 3R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R 4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D, 4G, 4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U Symbol CK CK DQx Type Input Input I/O Description Address, data in and control input register clock. Active high. Address, data in and control input register clock. Active low. Synchronous Data I/O.
G SA SBx
Input Input Input
Output Enable: Asynchronous pin, active low. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. Synchronous Chip Enable: Registered on the rising clock edge, active low. Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. Test Clock (JTAG). Test Data In (JTAG). Test Data Out (JTAG). Test Mode Select (JTAG). Enables sleep mode, active high. Core Power Supply. Output Power Supply: provides operating power for output buffers. Ground. No Connection: There is no connection to the chip. Note: 3J and 5J are tied common.
SS SW TCK TDI TDO TMS ZZ VDD VDDQ VSS NC
Input Input Input Input Output Input Input Supply Supply Supply --
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 3
MCM69L820A PIN DESCRIPTIONS
PBGA Pin Locations 4K 4L (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T 5L, 3G (a), (b) 4E 4M 4U 3U 5U 2U 7T 4C, 2J, 4J, 6J, 4R, 3R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R 4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G, 2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U Symbol CK CK DQx G SA SBx Type Input Input I/O Input Input Input Description Address, data in and control input register clock. Active high. Address, data in and control input register clock. Active low. Synchronous Data I/O. Output Enable: Asynchronous pin, active low. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. Synchronous Chip Enable: Registered on the rising clock edge, active low. Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. Test Clock (JTAG). Test Data In (JTAG). Test Data Out (JTAG). Test Mode Select (JTAG). Enables sleep mode, active high. Core Power Supply. Output Power Supply: provides operating power for output buffers. Ground. No Connection: There is no connection to the chip. Note: 3J and 5J are tied common.
SS SW TCK TDI TDO TMS ZZ VDD VDDQ VSS NC
Input Input Input Input Output Input Input Supply Supply Supply --
MCM69L738A*MCM69L820A 4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note 1)
Rating Core Supply Voltage Output Supply Voltage Voltage On Any Pin Input Current (per I/O) Output Current (per I/O) Power Dissipation (See Note 2) Operating Temperature Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin Iin Iout PD TA Tbias Tstg Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 - 0.5 to VDD + 0.5 50 70 -- 0 to + 70 - 10 to + 85 - 55 to + 125 Unit V V V mA mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. Power dissipation capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating Junction to Ambient (Still Air) Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board (Bottom) Junction to Case (Top) Single Layer Board Four Layer Board Symbol RJA RJA RJA RJB RJC Max 53 38 22 14 5 Unit C/W C/W C/W C/W C/W 3 4 Notes 1, 2 1, 2
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
CLOCK TRUTH TABLE
K CLK L-H L-H L-H L-H L-H L-H L-H L-H X ZZ L L L L L L L L H SS L L L L L L L H X SW H L L L L L L X X SBa X L H H H L H X X SBb X H L H H L H X X SBc X H H L H L H X X SBd X H H H L L H X X DQ (n) Dout 0-35 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DQ (n+1) X Din 0-8 Din 9-17 Din 18-26 Din 27-35 Din 0-35 High-Z X High-Z Mode Read Cycle All Bytes Write Cycle 1st Byte Write Cycle 2nd Byte Write Cycle 3rd Byte Write Cycle 4th Byte Write Cycle All Bytes Abort Write Cycle Deselect Cycle Sleep Mode
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Parameter Core Power Supply Voltage Output Driver Supply Voltage Active Power Supply Current Quiescent Active Power Supply Current Active Standby Power Supply Current Quiescent Standby Power Supply Current Sleep Mode Power Supply Current (x18) (x36) Symbol VDD VDDQ IDD1 IDD2 ISB1 ISB2 ISB3 Min 3.15 2.3 -- -- -- -- -- -- Typical -8.5 -- -- 320 370 180 170 150 30 Typical -9 -- -- 320 370 180 170 150 30 Typical -9.5 -- -- 300 350 180 170 150 30 Max 3.6 2.7 480 550 250 250 230 50 Unit V V mA mA mA mA mA 5 6, 10 7 8, 10 9, 10 Notes
NOTES: 1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps. 2. Supply voltage applied to VDD connections. 3. Supply voltage applied to VDDQ connections. 4. All power supply currents measured with outputs open or deselected. 5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles. 6. VDD = VDD (max), tKHKH = dc, SS registered active. 7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive. 8. VDD = VDD (max), tKHKH = dc, SS registered inactive. ZZ low. 9. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ high. 10. 200 mV Vin VDDQ - 200 mV.
DC INPUT CHARACTERISTICS
Parameter DC Input Logic High DC Input Logic Low Input Leakage Current Clock Input Leakage Current Clock Input Signal Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Range (See Figure 3) Symbol VIH (dc) VIL (dc) Ilkg Iclkg Vin VDIF(dc) VCM(dc) Min 1.7 - 0.3 -- -- - 0.3 0.2 1.1 Max VDD + 0.3 0.7 5 8 VDD + 0.3 VDD + 0.6 2.1 Unit V V A A V V V 3 4 1 2 2 Notes
NOTES: 1. Inputs may undershoot to - 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns). 2. 0 V Vin VDD for all pins. 3. Minimum instantaneous differential input voltage required for differential input clock operation. 4. Maximum rejectable common mode input voltage variation.
DC OUTPUT CHARACTERISTICS
Parameter Output Leakage Current Output Low Voltage Output High Voltage NOTES: 1. IOL = 8.0 mA. 2. IOH = - 8.0 mA. Symbol Ilkg VOL VOH Min - 1.0 -- 1.7 Max 1.0 0.7 -- Unit A V V 1 2 Notes
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0C TA 70C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance Input/Output Capacitance CK, CK Capacitance Symbol Cin CI/O CCK Typ 5 6 6 Max 5 8 7 Unit pF pF pF
MCM69L738A*MCM69L820A 6
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V Clock Input Timing Reference Level . . . . . . Differential Cross-Point Clock Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.1 V
READ/WRITE CYCLE TIMING (See Note 1)
MCM69L738A-8.5 MCM69L820A-8.5 Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Output Valid Clock Low to Output Valid Clock Low to Output Hold Clock Low to Output Low-Z Clock High to Output High-Z Output Enable Low to Output Low-Z Output Enable Low to Output Valid Output Enable to Output Hold Output Enable High to Output High-Z Setup Times: Address Data In Chip Select Write Enable Address Data In Chip Select Write Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tKLQV tKLQX tKLQX1 tKHQZ tGLQX tGLQV tGHQX tGHQZ tAVKH tDVKH tSVKH tWVKH tKHAX tKHDX tKHSX tKHWX Min 8 3.2 3.2 -- -- 0.5 1 1 0.5 -- 0.5 -- 0.5 Max -- -- -- 8.5 3.5 -- -- 3.5 -- 3.5 -- 3.5 -- MCM69L738A-9 MCM69L820A-9 Min 8 3.2 3.2 -- -- 0.5 1 1 0.5 -- 0.5 -- 0.5 Max -- -- -- 9 3.5 -- -- 3.5 -- 3.5 -- 3.5 -- MCM69L738A-9.5 MCM69L820A-9.5 Min 9 3.6 3.6 -- -- 0.5 1 1 0.5 -- 0.5 -- 0.5 Max -- -- -- 9.5 4 -- -- 4 -- 4 -- 4 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2 2, 3 2, 3 Notes N
Hold Times:
1
--
1
--
1
--
ns
NOTES: 1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications (e.g., tKHKL) or at frequencies that exceed the applied K clock frequency. 2. This parameter is sampled and not 100% tested. 3. Measured at 200 mV from steady state.
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 7
TIMING LIMITS
VDDQ/2 50 DEVICE UNDER TEST 50 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1. AC Test Load
VOH
VSS 50% 100% 20% tKHKH
Figure 2. Undershoot Voltage
VDDQ VTR CROSSING POINT VDIF VCP VSS *VCM, the Common Mode Input Voltage, equals VTR - ((VTR - VCP)/2). VCM*
Figure 3. Differential Inputs/Common Mode Input Voltage
MCM69L738A*MCM69L820A 8
MOTOROLA FAST SRAM
REGISTER LATCH READ-WRITE-READ CYCLES
t KHKH CK t AVKH t KHAX SA A0 A1 A2 t SVKH SS t WVKH t KHWX SW A3 t KHSX t KLKH A4 t KHKL
SBx
G t KHQV t KLQV t KLQX1 DQ Q0 READ t KHQZ
t KLQX t DVKH t KHDX Q1 READ D2 WRITE Q3 READ
t KHQZ t KLQX1 Q4 DESELECT (HIGH-Z) READ
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 9
REGISTER LATCH READ-WRITE-READ CYCLES (G Controlled)
CK
SA
A0
A1
A2
A3
A4
SS
SW
SBx
G
t GLQV t GLQX
t GHQX
DQ
Q0 READ
Q1 READ
D2 WRITE
Q3 READ DESELECT (HIGH-Z)
Q4 READ
MCM69L738A*MCM69L820A 10
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FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS All control signals except G are registered on the rising edge of the CK clock. These signals must meet the setup and hold times shown in the AC Characteristics table. On the falling edge of the current cycle, the output latch becomes transparent and data is available. The output data is latched on the rising edge of the next clock. The output data is available at the output at tKLQV or tKHQV, whichever is later. tKHQV is the internal latency of the device. During this same cycle a new read address can be applied to the address pins. A write cycle can occur on the next cycle as long as tKLQX and tDVKH are met. Read cycles may follow write cycles immediately. G, SS, and SW control output drive. Chip deselect via a high on SS at the rising edge of the CK clock has its effect on the output drivers immediately. SW low deselects the output drivers immediately (on the same cycle). Output selecting via a low on SS and high on SW at a rising CK clock has its effect on the output drivers at tKLQX. Output drive is also controlled directly by output enable, G. G is an asynchronous input. No clock edges are required to enable or disable the output with G. Output data will be valid the later of tGLQV, tKHQV, or tKLQV. Outputs will begin driving at tKLQX1. Outputs will hold previous data until tKLQX or tGHQX. WRITE AND BYTE WRITE FUNCTIONS Note that in the following discussion the term "byte" refers to nine bits of the RAM I/O bus. In all cases, the timing parameters described for synchronous write input (SW) apply to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles. This allows the system designer not interested in performing byte writes to connect the byte enable inputs to active low (VSS). Reads of all bytes proceed normally and write cycles, activated via a low on SW, and the rising edge of the CK clock, write the entire RAM I/O width. This way the designer is spared having to drive multiple write input buffer loads. Byte writes are performed using the byte write enable inputs in conjunction with the synchronous write input (SW). It is important to note that writing any one byte will inhibit a read of all bytes at the current address. The RAM can not simultaneously read one byte and write another at the same address. A write cycle initiated with none of the byte write enable inputs active is neither a read or a write. No write will occur, but the outputs will be deselected as in a normal write cycle. LATE WRITE The write address is sampled on the first rising edge of clock and write data is sampled on the following rising edge. The late write feature is implemented with single stage write buffering. Write buffering is transparent to the user. A comparator monitors the address bus and, when necessary, routes buffer contents to the outputs to assure coherent operation. This occurs in all cases whether there is a byte write or a full word is written. POWER UP AND INITIALIZATION Please note, per the Absolute Maximum Ratings table, V D D Q is not to exceed V D D + 0.5 V, whatever the instantaneous value of VDD. Once supplies have reached specification levels, a minimum dwell of 1.0 s with CK clock inputs cycling is required before beginning normal operations.
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 11
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture. (The TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with Standard 1149.1 compliant TAPs. The TAP operates using conventional JEDEC Standard 8-1B Low Voltage (3.3 V) TTL/ CMOS logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 k resistor. TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted)
Parameter Logic Input Logic High Logic Input Logic Low Logic Input Leakage Current CMOS Output Logic Low CMOS Output Logic High TTL Output Logic Low TTL Output Logic High NOTES: 1. 0 V Vin VDDQ for all logic input pins. 2. IOL1 100 A @ VOL = 0.2 V. Sampled, not 100% tested. 3. IOH1 100 A @ VDDQ - 0.2 V. Sampled, not 100% tested. 4. IOL2 8 mA @ VOL = 0.4 V. 5. IOH2 8 mA @ VOH = 2.4 V. Symbol VIH1 VIL1 Ilkg VOL1 VOH1 VOL2 VOH2 Min 2.0 - 0.3 -- -- VDD - 0.2 -- 2.4 Max VDD + 0.3 0.8 5 0.2 -- 0.4 -- Unit V V A V V V V 1 2 3 4 5 Note
MCM69L738A*MCM69L820A 12
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TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Test Load . . . . . . 50 Parallel Terminated T-line with 20 pF Receiver Input Capacitance Test Load Termination Supply Voltage (VT) . . . . . . . . . . . . . . . 1.5 V
TAP CONTROLLER TIMING
Parameter Cycle Time Clock High Time Clock Low Time TMS Setup TMS Hold TDI Valid to TCK High TCK High to TDI Don't Care Capture Setup Capture Hold TCK Low to TDO Unknown TCK Low to TDO Valid Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQX tTLOV Min 100 40 40 10 10 10 10 10 10 0 -- Max -- -- -- -- -- -- -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Notes
NOTES: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.
AC TEST LOAD
1.5 V 50 DEVICE UNDER TEST 50 20 pF
TAP CONTROLLER TIMING DIAGRAM
tTHTH tTLTH TEST CLOCK (TCK) tTHTL tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV tTLQX TEST DATA OUT (TDO) tTHMX
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MCM69L738A*MCM69L820A 13
TEST ACCESS PORT PINS
TCK -- TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS -- TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. TDI -- TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 5, TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDO -- TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (refer to Figure 5, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST -- TAP RESET This device does not have a TRST pin. TRST is optional in IEEE 1149.1. The test-logic reset state is entered while TMS is held high for five rising edges of TCK. Power on reset circuitry is included internally. This type of reset does not affect the operation of the system logic. The reset affects test logic only.
BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 1) reserved for density upgrade address pins. There are a total of 70 bits in the case of the x36 device and 51 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary scan register. The Bump/Bit Scan Order tables describe which device bump connects to each boundary scan register location. The first column defines the bit's position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator
Bit No. Value 0 1
TEST ACCESS PORT REGISTERS
OVERVIEW The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected it is "placed" between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in test-logic- reset state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible.
Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1 - 1990
Bit No. Value 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0
Reserved For Future Use
Bit No. Value 17 x 16 x 15 x 14 x 13 x 12 x
Device Width
Configuration 128K x 36 256K x 18 Bit No. Value Value 22 0 0 21 0 0 20 1 0 19 0 1 18 0 1
Device Depth
Configuration 128K x 36 256K x 18 Bit No. Value Value 27 0 0 26 0 0 25 1 1 24 0 1 23 1 0
Revision Number
Bit No. Value 31 x 30 x 29 x 28 x
Figure 4. ID Register Bit Meanings
MCM69L738A*MCM69L820A 14
MOTOROLA FAST SRAM
MCM69L738A Bump/Bit Scan Order
Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name M2 SA SA SA SA ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa SBa CK CK G SBb DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA SA NC SA Bump ID 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name SA NC SA SA SA SA DQc DQc DQc DQc DQc DQc DQc DQc DQc SBc NC SS NC NC SW SBd DQd DQd DQd DQd DQd DQd DQd DQd DQd SA SA SA M1 Bump ID 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R
MCM69L820A Bump/Bit Scan Order
Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name M2 SA SA SA SA ZZ DQa DQa DQa DQa SBa CK CK G DQa DQa DQa DQa DQa SA SA SA SA NC SA SA NC SA SA SA SA DQb DQb DQb DQb Bump ID 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 1D 2E 2G 1H Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name SBb NC SS NC NC SW DQb DQb DQb DQb DQb SA SA SA SA M1 Bump ID 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R
NOTES: 1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a "place holder" bit that is forced to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard. 2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation. 3. M1 and M2 are not ordinary inputs and may not respond to standard I/O logic levels. M1 and M2 must be driven to within 100 mV of a VDD or VSS supply rail to ensure consistent results. 4. ZZ must remain at VIL during boundary scan to ensure consistent results.
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 15
TAP CONTROLLER INSTRUCTION SET
OVERVIEW There are two classes of instructions defined in Standard 1149.1-1990; the standard (public) instructions, and device specific (private) instructions. Some public instructions, are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/ PRELOAD command. When the TAP controller is placed in capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift-IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update-IR state. The TAP instruction sets for this device are listed in the following tables.
expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the pause-DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not IEEE 1149.1 compliant. Nevertheless, this RAMs TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register the RAM responds just as it does in response to the SAMPLE/PRELOAD instruction described above, except the RAM outputs are forced to High-Z any time the instruction is loaded. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (High-Z) and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state.
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NOOP Do not use these instructions; they are reserved for future use.
MCM69L738A*MCM69L820A 16
MOTOROLA FAST SRAM
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction EXTEST IDCODE SAMPLE / PRELOAD Code* 000 001** 100 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all RAM outputs to High-Z state. NOT IEEE 1149.1 COMPLIANT. Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1 COMPLIANT. Places bypass register between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all RAM output drivers to High-Z state.
BYPASS SAMPLE-Z
111 010
* Instruction codes expressed in binary, MSB on left, LSB on right. ** Default instruction automatically loaded at power-up and in test-logic-reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction NO OP NO OP NO OP Code* 011 101 110 Description Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
1
TEST-LOGIC RESET 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 0 1 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 1 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 0 1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 17
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
69L738A 69L820A XX
X
X
R = Tape and Reel, Blank = Tray Speed (8.5 = 8.5 ns, 9 = 9 ns, 9.5 = 9.5 ns) Package (ZP = PBGA)
Full Part Numbers -- MCM69L738AZP8.5 MCM69L820AZP8.5 MCM69L738AZP8.5R MCM69L820AZP8.5R
MCM69L738AZP9 MCM69L820AZP9 MCM69L738AZP9R MCM69L820AZP9R
MCM69L738AZP9.5 MCM69L820AZP9.5 MCM69L738AZP9.5R MCM69L820AZP9.5R
MCM69L738A*MCM69L820A 18
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
ZP PACKAGE 7 X 17 BUMP PBGA CASE 999-01
4X PIN 1A IDENTIFIER
0.20 (0.008)
A -W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER.
7 6 54 3 2 1 A B C D E F G H J K L M N P R T U
P
B -L-
S
16X
G
DIM A B C D E F G K N P R S 119X
MILLIMETERS MIN MAX 14.00 BSC 22.00 BSC --- 2.40 0.60 0.90 0.50 0.70 1.30 1.70 1.27 BSC 0.80 1.00 11.90 12.10 19.40 19.60 7.62 BSC 20.32 BSC
INCHES MIN MAX 0.551 BSC 0.866 BSC --- 0.094 0.024 0.035 0.020 0.028 0.051 0.067 0.050 BSC 0.031 0.039 0.469 0.476 0.764 0.772 0.300 BSC 0.800 BSC
N TOP VIEW
6X
G R BOTTOM VIEW
D 0.30 (0.012) 0.10 (0.004)
S S
TW T
S
L
S
F C
0.25 (0.010) T 0.35 (0.014) T 0.15 (0.006) T -T- K E SIDE VIEW
MOTOROLA FAST SRAM
MCM69L738A*MCM69L820A 19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MCM69L738A*MCM69L820A 20
MOTOROLAMCM69L738A/D FAST SRAM

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